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| 8-Bit CMOS Microcontroller GMS90 Series GMS90C31/51/31B/51B, GMS97C51 GMS90L31/51/31B/51B, GMS97L51 (Low voltage versions) Fully compatible to standard MCS-51 microcontroller Versions for 12/24/40 MHz operating frequency (90C31/51) Versions for 12/24/33 MHz operating frequency (90C31B/51B, 97C51) Low voltage versions are available 12MHz only 4K x 8 (EP)ROM 128 x 8 RAM 64K external program memory space 64K external data memory space Four 8-bit ports Two 16-bit Timers / Counters USART Five interrupt sources, two priority levels Power saving Idle and power down mode Quick pulse programming algorithm (in the OTP devices) 2-level program memory lock (in the OTP devices) 2.7Volt low voltage version available P-DIP-40, P-LCC-44, P-MQFP-44 package RAM 128 x 8 T0 CPU T1 ROM / EPROM 4K x 8 8-BIT USART PORT 0 PORT 1 PORT 2 I/O I/O I/O PORT 3 I/O Block Diagram MAY. 1998 1 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller GMS90C32/52/32B/52B, GMS97C52 GMS90L32/52/32B/52B, GMS97L52 (Low voltage versions) Fully compatible to standard MCS-51 microcontroller Versions for 12/24/40 MHz operating frequency (90C32/52) Versions for 12/24/33 MHz operating frequency (90C32B/52B, 97C52) Low voltage versions are available 12MHz only 8K x 8 (EP)ROM 256 x 8 RAM 64K external program memory space 64K external data memory space Four 8-bit ports Three 16-bit Timers / Counters (Timer2 with up/down counter feature) USART Six interrupt sources, two priority levels Power saving Idle and power down mode Quick pulse programming algorithm (in the OTP devices) 2-level program memory lock (in the OTP devices) 2.7Volt low voltage version available P-DIP-40, P-LCC-44, P-MQFP-44 package RAM 256 x 8 T0 T2 T1 ROM / EPROM 8K x 8 CPU 8-BIT USART PORT 0 PORT 1 PORT 2 I/O I/O I/O PORT 3 I/O Block Diagram LG Semicon MCU 2 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series GMS90C54/56/58, GMS97C54/56/58 GMS90L54/56/58, GMS97L54/56/58 (Low voltage versions) Fully compatible to standard MCS-51 microcontroller Versions for 12/24/33 MHz operating frequency Low voltage versions are available 12MHz only 16K/24K/32K bytes (EP)ROM 256 x 8 RAM 64K external program memory space 64K external data memory space Four 8-bit ports Three 16-bit Timers / Counters (Timer2 with up/down counter feature) USART One clock output port Programmable ALE pin enable / disable Six interrupt sources, two priority levels Power saving Idle and power down mode Quick pulse programming algorithm (in the OTP devices) 2-level program memory lock (in the OTP devices) 2.7Volt low voltage version available (with 12MHz operating frequency) P-DIP-40, P-LCC-44, P-MQFP-44 package RAM 256 x 8 T0 T2 T1 CPU 8-BIT USART PORT 0 PORT 1 PORT 2 I/O I/O I/O ROM: GMS9xC54: 16K x 8 GMS9xC56: 24K x 8 GMS9xC58: 32K x 8 PORT 3 I/O Block Diagram MAY. 1998 3 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller GMS90 series Selection Guide Operating voltage (V) (EP)ROM (bytes) RAM (bytes) 128 128 256 256 128 128 256 256 256 256 256 128 256 256 256 256 128 128 256 256 128 128 256 256 256 256 256 128 256 256 256 256 Device GMS90C31 GMS90C31B GMS90C32 GMS90C32B GMS90C51 GMS90C51B GMS90C52 GMS90C52B *GMS90C54 *GMS90C56 *GMS90C58 GMS97C51 GMS97C52 GMS97C54 GMS97C56 GMS97C58 GMS90L31 GMS90L31B GMS90L32 GMS90L32B GMS90L51 GMS90L51B GMS90L52 GMS90L52B *GMS90L54 *GMS90L56 *GMS90L58 GMS97L51 GMS97L52 GMS97L54 GMS97L56 GMS97L58 Frequency (MHz) 12/24/40 12/24/33 12/24/40 12/24/33 12/24/40 12/24/33 12/24/40 12/24/33 " " " 12/24/33 " " " " ROM-less 4.25~5.5 4K 4K 8K 8K 16K 24K 32K 4K OTP 8K OTP 16K OTP 24K OTP 32K OTP ROM-less 12 2.7~5.5 4K 4K 8K 8K 16K 24K 32K 4K OTP 8K OTP 16K OTP 24K OTP 32K OTP 12 12 Note) * : Under development LG Semicon MCU 4 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series 44-PLCC Pin Configuration (top view) (P-LCC-44) MAY. 1998 5 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller 40-PDIP Pin Configuration (top view) (P-DIP-40) LG Semicon MCU 6 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series 44-MQFP Pin Configuration (top view) (P-MQFP-44) MAY. 1998 7 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Logic Symbol LG Semicon MCU 8 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Pin Definitions and Functions Symbol P1.0 - P1.7 Pin Number P-LCC-44 2-9 P-DIP-40 1-8 P-MQFP-44 40-44, 1-3 Input/ Output I/O Function Port1 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the pulls-ups (IIL, in the DC characteristics). Pins P1.0 and P1.1 also. Port1 also receives the low-order address byte during program memory verification. Port1 also serves alternate functions of Timer 2. P1.0 / T2 : Timer/counter 2 external count input P1.1 / T2EX : Timer/counter 2 trigger input In GMS9xC54/56/58: P1.0 / T2, Clock Out : Timer/counter 2 external count input, Clock Out 2 3 2 P3.0 - P3.7 11, 13-19 1 2 1 10-17 40 41 40 5, 7-13 I/O Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 3 pins that are externally pulled low will source current because of the pulls-ups (IIL, in the DC characteristics). Port 3 also serves the special features of the 80C51 family, as listed below. P3.0 / RxD receiver data input (asynchronous) or data input output(synchronous) of serial interface 0 P3.1 / TxD transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 P3.2 / INT0 interrupt 0 input/timer 0 gate control P3.3 / INT1 interrupt 1 input/timer 1 gate control P3.4 / T0 counter 0 input P3.5 / T1 counter 1 input P3.6 / WR the write control signal latches the data byte from port 0 into the external data memory P3.7 / RD the read control signal enables the external data memory to port 0 11 10 5 13 11 7 14 15 16 17 18 12 13 14 15 16 8 9 10 11 12 19 XTAL2 20 17 18 13 14 O XTAL2 Output of the inverting oscillator amplifier. MAY. 1998 9 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Symbol XTAL1 Pin Number P-LCC-44 21 P-DIP-40 19 P-MQFP-44 15 Input/ Output I Function XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 2 pins that are externally pulled low will source current because of the pulls-ups (IIL, in the DC characteristics).Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses(MOVX @DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 special function register. The Program Store Enable The read strobe to external program memory when the device is executing code from the external program memory. PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VCC. P2.0 - P2.7 24-31 21-28 18-25 I/O PSEN 32 29 26 O RESET 10 9 4 I LG Semicon MCU 10 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Symbol ALE / PROG Pin Number P-LCC-44 33 P-DIP-40 30 P-MQFP-44 27 Input/ Output O Function The Address Latch Enable / Program pulse Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input(PROG) during EPROM programming. In GMS9xC54/56/58: If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With this bit set, the pin is weakly pulled high. The ALE disable feature will be terminated by reset. Setting the ALE-disable bit has no affect if the microcontroller is in external execution mode. External Access Enable / Program Supply Voltage EA must be external held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than its internal memory size. This pin also receives the 12.75V programming supply voltage(VPP) during EPROM programming. Note; however, that if any of the Lock bits are programmed, EA will be internally latched on reset. Port 0 Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the GMS97C5x. External pull-up resistors are required during program verification. Circuit ground potential Supply terminal for all operating modes No connection EA / VPP 35 31 29 I P0.0 - P0.7 43-36 39-32 37-30 I/O VSS VCC N.C. 22 44 1,12, 23,34 20 40 - 16 38 6,17,28,39 - MAY. 1998 11 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Functional Description The GMS90 series is fully compatible to the standard 8051 microcontroller family. It is compatible with the general 8051 family. characteristics of the general 8051 family. While maintaining all architectural and operational Figure 1 shows a block diagram of the GMS90 series 4/8/1624/32K Figure 1 Block Diagram of the GMS90 series LG Semicon MCU 12 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series CPU The GMS90 series is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0A. Special Function Register PSW MSB Bit No. Addr. D0H 7 CY 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 F1 LSB 0 P PSW Reset value of PSW is 00H. Bit CY AC F0 RS1 0 0 1 1 OV F1 P RS0 0 1 0 1 Carry Flag Auxiliary Carry Flag (for BCD operations) General Purpose Flag Register Bank select control bits Bank 0 selected, data address 00H - 07H Bank 1 selected, data address 08H - 0FH Bank 2 selected, data address 10H - 17H Bank 3 selected, data address 18H - 1FH Overflow Flag General Purpose Flag Parity Flag Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. Function MAY. 1998 13 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 27 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All SFRs are listed in table 1, table 2, and table 3. In table 1 they are organized in numeric order of their addresses. In table 2 they are organized in groups which refer to the functional blocks of the GMS90 series. Table 3 illustrates the contents of the SFRs. Table 1 Special Function Registers in Numeric Order of their Addresses Address 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 3) 8FH 90H 91H 92H 93H 94H 95H 96H 97H 1) 2) 3) Register P01) SP DPL DPH reserved reserved reserved PCON TCON1) TMOD TL0 TL1 TH0 TH1 F 3) reserved P11) reserved reserved reserved reserved reserved reserved reserved Contents after Reset FFH 07H 00H 00H XXH2) XXH2) XXH2) 0XXX000B2) 00H 00H 00H 00H 00H 00H F 3) XXH2) FFH 00H XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) Address 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH Register SCON1) SBUF reserved reserved reserved reserved reserved reserved P21) reserved reserved reserved reserved reserved reserved reserved IE1) reserved reserved reserved reserved reserved reserved reserved Contents after Reset 00H XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) FFH XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) 0X000000B2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) : Bit-addressable Special Function Register. : X means that the value is indeterminate and the location is reserved. : The GMS9xC54/56/58 have the AUXR0 register at address 8EH. GMS9xC51/52 GMS9xC54/56/58 8EH reserved XXH 2) 8EH AUXR0 1) XXXXXXX0B 2) LG Semicon MCU 14 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Special Function Registers in Numeric Order of their Addresses (continued) Address B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H3) CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H 1) 2) Register P31) reserved reserved reserved reserved reserved reserved reserved IP1) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved T2CON T2MOD RC2L RC2H TL2 TH2 reserved reserved PSW1) reserved reserved reserved reserved reserved reserved reserved Contents after Reset FFH XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XX000000B2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) 00H F 3) 00H 00H 00H 00H XXH2) XXH2) 00H XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) Address D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH Register reserved reserved reserved reserved reserved reserved reserved reserved ACC1) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved B1) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Contents after Reset XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) 00H XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) 00H XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) : Bit-addressable Special Function Register : X means that the value is indeterminate and the location is reserved 3) : GMS9xC54/56/58 GMS9xC51/52 C9H T2MOD XXXXXXX0H 2) C9H T2MOD XXXXXX00B 2) MAY. 1998 15 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Table 2 Special Function Registers - Functional Blocks Block Symbol Name Address E0H1) F0H1) 83H 82H D0H1) 81H A8H1) B8H1) 80H1) 90H1) A0H1) B0H1) 87H 99H 98H1) 88H1) 8CH 8DH 8AH 8BH 89H C8H1) C9H CBH CAH CDH CCH 8EH 87H Contents after Reset 00H 00H 00H 00H 00H 07H 0X000000B2) XX000000B2) FFH XXH3) FFH FFH 0XXX0000B2) XXH3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H XXXXXXX0B 2) 0XXX0000B2) CPU ACC B DPH DPL PSW SP IE IP P0 P1 P2 P3 PCON2) SBUF SCON TCON TH0 TH1 TL0 TL1 TMOD T2CON T2MOD RC2H RC2L TH2 TL2 AUXR0 4) PCON Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Interrupt Enable Register Interrupt Priority Register Port 0 Port 1 Port 2 Port 3 Power Control Register Serial Channel Buffer Reg. Serial Channel 0 Control Reg. Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload Capture Reg., High Byte Timer 2 Reload Capture Reg., Low Byte Timer 2, High Byte Timer 2, Low Byte Aux. Register 0 Power Control Register Interrupt System Ports Serial Channels Timer 0 / Timer 1 Timer 2 Power Saving Modes 1) 2) Bit-addressable Special Function register This special function register is listed repeatedly since some bit of it also belong to other functional blocks 3) X means that the value is indeterminate and the location is reserved 4) : The AUXR0 is in the GMS9xC54/56/58 only. LG Semicon MCU 16 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Table 3 Contents of SFRS, SFRS in Numeric Order Address 80H 81H 82H 83H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 90H 98H 99H A0H A8H B0H B8H C8H C9H Register P0 SP DPL DPH PCON TCON TMOD TL0 TL1 TH0 TH1 AUXR0 1) P1 SCON SBUF P2 IE P3 IP T2CON T2MOD TF2 EXF2 PT2 RCLK PS TCLK PT1 EXEN2 PX1 TR2 PT0 C/T2 T2OE 1) Bit7 6 5 4 3 2 1 0 SMOD TF1 GATE TR1 C/T TF0 M1 TR0 M0 GF1 IE1 GATE GF0 IT1 C/T PDE IE0 M1 IDLE IT0 M0 - - - - - - - A0 1) SM0 SM1 SM2 REN TB8 RB8 TI RI EA - ET2 ES ET1 EX1 ET0 EX0 PX0 CP/RL2 DCEN SFR bit and byte addressable SFR not bit addressable - : this bit location is reserved 1) Only in the GMS9xC54/56/58 MAY. 1998 17 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Table 3 Contents of SFRS, SFRS in Numeric Order (continued) Address CAH CBH CCH CDH D0H E0H F0H Register RC2L RC2H TL2 TH2 PSW ACC B CY AC F0 RS1 RS0 OV F1 P Bit7 6 5 4 3 2 1 0 SFR bit and byte addressable SFR not bit addressable - : this bit location is reserved LG Semicon MCU 18 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4: Table 4 Timer/Counter 0 and 1 Operating Modes TMOD Mode 0 1 2 3 Input Clock M0 0 1 0 internal fOSC/ 1232 fOSC/ 12 fOSC/ 12 external (max) fOSC/ 2432 fOSC/ 24 fOSC/ 24 Description 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit autoreload Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops Gate C/T X X X X X X M1 0 0 1 X X 1 1 fOSC/ 12 fOSC/ 23 In the "timer" function (C/T = "0") the register is incremented every machine cycle. therefore the count rate is fOSC/12. In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 2 illustrates the input clock logic. Figure 2 Timer/Counter 0 and 1 Input Clock Logic MAY. 1998 19 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Timer 2 Timer 2 is a 16-bit timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in table 5. Table 5 Timer/Counter 2 Operating Modes T2CON Mode RxCLK or TxCLK 0 0 0 0 16-bit Capture CP/ RL2 TR2 T2MOD T2CON P1.1/ T2EX Remarks Input Clock internal external (P1.0/T2) DCEN 0 0 0 0 1 1 1 1 0 0 1 1 EXEN 0 1 X X X e 0 1 reload upon overflow reload trigger (falling edge) Down counting Up counting 16 bit Timer/ Counter (only up-counting) capture TH2, TL2 ae RC2H, RC2L no overflow interrupt request (TF2) extra external interrupt ("Timer 2") 16-bit Autoreload fOSC/ 12 max fOSC/ 24 0 0 1 1 1 1 X X 0 1 X e fOSC/ 12 max fOSC/ 24 Baud Rate Generator 1 1 X X 1 1 X X 0 1 X e fOSC/ 2 max fOSC/ 24 off X X 0 X X X Timer 2 stops - - LG Semicon MCU 20 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 6. The possible baud rates can be calculated using the formulas given in table 7. Table 6 USART Operating Modes SCON SM0 0 0 SM1 0 fOSC/ 12 Serial data enters and exits through RxD. TxD outputs the shift clock. 8-bit are transmitted/received (LSB first) 8-bit UART 10 bits are transmitted (through TxD) or received (RxD) 9-bit UART 11bits are transmitted (TxD) or received (RxD) 9-bit UART Like mode 2 except the variable baud rate Mode Baud rate Description 1 0 1 Timer 1/2 overflow rate 2 1 0 fOSC/ 32 or fOSC/ 64 3 1 1 Timer 1/2 overflow rate Table 7 Formulas for Calculating Baud rates Baud Rate derived from Oscillator Timer 1 (16-bit timer) (8-bit timer with 8-bit autoreload) Timer2 Interface Mode 0 2 1,3 1,3 1,3 Baud rate fOSC/ 12 (2SMOD fOSC) / 64 (2SMOD timer 1 overflow rate) /32 (2SMOD fOSC ) /(3212(256-TH1)) fOSC / (32 (65536-(RC2H, RC2L) MAY. 1998 21 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Interrupt System The GMS90 series provides 5 or 6 interrupt sources with two priority levels. Figure 3 gives a general overview of the interrupt sources and illustrates the request and control flags. Figure 3 Interrupt Request Sources LG Semicon MCU 22 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Table 8 Interrupt Sources and their Corresponding Interrupt Vectors Source (Request Flags) RESET IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 Vector RESET External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt 0000H 0003H 000BH 0013H 001BH 0023H 002BH Vector Address A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 9. Table 9 Interrupt Priority-Within-Level Interrupt Source External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Serial Channel Timer 2 Interrupt IE0 TF0 IE1 TF1 RI + TI TF2 EXF2 Priority High e e e e Low MAY. 1998 23 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Power Saving Modes Two power down modes are available, the Idle Mode and Power Down Mode. The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 10 gives a general overview of the power saving modes. Table 10 Power Saving Modes Overview Entering Instruction Example ORL PCON, #01H Mode Leaving by Remarks CPU is gated off CPU status registers maintain their data. Peripherals are active Oscillator is stopped, contents of on-chip RAM and SFRs are maintained (leaving Power Down Mode means redefinition of SFR contents). Idle mode - Enabled interrupt - Hardware Reset Power-down Mode ORL PCON, #02H Hardware Reset In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the Power Down Mode is invoked, and that VCC is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power Down Mode also restarts the oscillator. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). LG Semicon MCU 24 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Absolute Maximum Ratings Ambient temperature under bias (TA) ..............................................................-40 to + 85E Storage temperature (TST) ..............................................................................-65 to + 150 E Voltage on VCC pins with respect to ground (VSS) .........................................-0.5 V to 6.5 V Voltage on any pin with respect to ground (VSS) ............................................-0.5 to VCC + 0.5 V Input current on any pin during overload condition .......................................-10 mA to + 10 mA Absolute sum of all input currents during overload condition ........................ | 100 mA | Power dissipation ............................................................................................TBD Note : Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. MAY. 1998 25 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller DC Characteristics for GMS90C31/32, GMS90C51/52 GMS90C31B/32B, GMS90C51B/52B VCC = 5 V + 10%, - 15%; VSS = 0 V; TA = 0E to 70E Limit Values min. Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Input high voltage (except XTAL1, EA, RESET) Input high voltage to XTAL1 Input high voltage to EA, RESET Output low voltage (ports 1, 2, 3) Output high voltage (port 0, ALE, PSEN) Output high voltage (ports 1, 2, 3) Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 12MHz 6) Idle mode, 12MHz 6) Active mode, 24 MHz 6) Idle mode, 24MHz 6) Active mode, 33 MHz 6) Idle mode, 33 MHz 6) Active mode, 40 MHz 6) Idle mode, 40 MHz 6) Power Down Mode VIL VIL 1 VIL 2 VIH VIH 1 VIH 2 VOL VOL 1 VOH -0.5 -0.5 -0.5 0.2VCC + 0.9 0.7VCC 0.6VCC 2.4 0.9 VCC 2.4 0.9VCC -10 -65 -50 -650 1 10 Parameter Symbol Unit Test Condition max. 0.2 V CC - 0.1 0.2 V CC - 0.3 0.2 V CC + 0.1 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.45 0.45 V V V V V V V V V IOL = 1.6mA1) IOL = 3.2mA1) IOH = - 80 E IOH = - 10 E IOH = - 800 E2) IOH = - 80 E2) VIN = 0.45V VIN = 2V 0.45 < VIN < VCC fC = 1MHz TA = 25E VCC = 5V 4) VCC = 5V 5) VCC = 5V 4) VCC = 5V 5) VCC = 5V 4) VCC = 5V 5) VCC = 5V 4) VCC = 5V 5) VCC = 5V 3) VOH 1 V IIL ITL ILI CIO E E E pF ICC ICC ICC ICC ICC ICC ICC ICC IPD - 21 4.8 36.2 8.2 45 10 56.5 12.5 50 mA mA mA mA mA mA mA mA E LG Semicon MCU 26 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series DC Characteristics for GMS90C54/56/58 VCC = 5 V + 10%, - 15%; VSS = 0 V; TA = 0E to 70E Limit Values min. max. 0.2 VCC - 0.1 0.2 VCC - 0.3 0.2 VCC + 0.1 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.45 0.45 -50 -650 1 10 V V V V V V V V V IOL = 1.6mA1) IOL = 3.2mA1) IOH = - 80 E IOH = - 10 E IOH = - 800 E2) IOH = - 80 E2) VIN = 0.45V VIN = 2V 0.45 < VIN < VCC fC = 1MHz TA = 25E VCC = 5V 4) VCC = 5V 5) VCC = 5V 4) VCC = 5V 5) VCC = 5V 4) VCC = 5V 5) VCC = 5V 3) Parameter Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Input high voltage (except XTAL1, EA, RESET) Input high voltage to XTAL1 Input high voltage to EA, RESET Output low voltage (ports 1, 2, 3) Output high voltage (port 0, ALE, PSEN) Output high voltage (ports 1, 2, 3) Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 12MHz 6) Idle mode, 12MHz 6) Active mode, 24 MHz 6) Idle mode, 24MHz 6) Active mode, 33 MHz 6) Idle mode, 33 MHz 6) Power Down Mode Symbol Unit Test Condition VIL VIL 1 VIL 2 VIH VIH 1 VIH 2 VOL VOL 1 VOH -0.5 -0.5 -0.5 0.2VCC + 0.9 0.7VCC 0.6VCC 2.4 0.9 VCC 2.4 0.9VCC -10 -65 VOH 1 V IIL ITL ILI CIO E E E pF ICC ICC ICC ICC ICC ICC IPD - TBD TBD TBD TBD TBD TBD 50 mA mA mA mA mA mA E MAY. 1998 27 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller DC Characteristics for GMS97C51/52/54/56/58 VCC = 5 V + 10%, - 15%; VSS = 0 V; TA = 0E to 70E Limit Values min. Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Input high voltage (except XTAL1, EA, RESET) Input high voltage to XTAL1 Input high voltage to EA, RESET Output low voltage (ports 1, 2, 3) Output high voltage (port 0, ALE, PSEN) Output high voltage (ports 1, 2, 3) Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 12 MHz 6) Idle mode, 12 MHz 6) Active mode, 24 MHz 6) Idle mode, 24 MHz 6) Active mode, 33 MHz 6) Idle mode, 33 MHz 6) Power down mode VIL VIL 1 VIL 2 VIH VIH 1 VIH 2 VOL VOL 1 VOH -0.5 -0.5 -0.5 0.2VCC + 0.9 0.7VCC 0.6VCC 2.4 0.9 VCC 2.4 0.9VCC -10 -65 -50 -650 1 10 Parameter Symbol Unit Test Condition max. 0.2 V CC - 0.1 0.1 V CC - 0.1 0.2 V CC + 0.1 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.45 0.45 V V V V V V V V V IOL = 1.6mA1) IOL = 3.2mA1) IOH = - 80 E IOH = - 10 E IOH = - 800 E2) IOH = - 80 E2) VIN = 0.45V VIN = 2V 0.45 < VIN < VCC fC = 1MHz TA = 25E VCC = 5V 4) VCC = 5V 5) VCC = 5V 4) VCC = 5V 5) VCC = 5V 4) VCC = 5V 5) VCC = 5V 3) VOH 1 V IIL ITL ILI CIO E E E pF ICC ICC ICC Icc ICC Icc IPD - 21 18 36 20 47 25 50 mA mA mA mA mA mA E LG Semicon MCU 28 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series DC Characteristics for GMS90L31/32, GMS90L51/52, GMS90L31B/32B, GMS90L51B/52B (Low voltage version) VCC = 3.3 V + 0.3V, - 0.6V; VSS = 0 V; TA = 0E to 70E Limit Values min. Input low voltage Input high voltage Output low voltage Port 1,2,3 Port 0,EA,RESET Port 1,2,3 Port 0,EA,RESET Output high voltage Port 1,2,3 Port 0 in external bus mode, ALE,PSEN Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 12 MHz Idle mode, 12 MHz Power Down Mode VIL VIH VOL 1 VOL 2 VOL 3 VOL 4 VOH 1 VOH 2 VOH 3 VOH 4 IIL ITL ILI CIO -0.5 2.0 2.0 0.9VCC 2.0 0.9VCC -1 -25 0.8 VCC + 0.5 0.45 0.45 0.3 0.3 -50 -250 1 10 Parameter Symbol Unit V V V V V V V V V V E E E pF Test Condition IOL = 1.6mA 1) IOL = 3.2mA 1) IOL = 100E 1) IOL = 200E 1) IOH = IOH = IOH = IOH = -20E -10E -800E 2) -80E 2) max. VIN = 0.45V VIN = 2.0V 0.45 < VIN < VCC fC = 1MHz TA = 25E VCC = 3.6V 4) VCC = 3.6V 5) VCC = 2 ... 3.6V 3) ICC ICC IPD - 11 5 15 mA mA E MAY. 1998 29 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller DC Characteristics for GMS90L54/56/58 (Low voltage version) VCC = 3.3 V + 0.3V, - 0.6V; VSS = 0 V; TA = 0E to 70E Limit Values min. Input low voltage Input high voltage Output low voltage Port 1,2,3 Port 0,EA,RESET Port 1,2,3 Port 0,EA,RESET Output high voltage Port 1,2,3 Port 0 in external bus mode, ALE,PSEN Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 12 MHz Idle mode, 12 MHz Power Down Mode VIL VIH VOL 1 VOL 2 VOL 3 VOL 4 VOH 1 VOH 2 VOH 3 VOH 4 IIL ITL ILI CIO -0.5 2.0 2.0 0.9VCC 2.0 0.9VCC -1 -25 0.8 VCC + 0.5 0.45 0.45 0.3 0.3 -50 -250 1 10 Parameter Symbol Unit V V V V V V V V V V E E E pF Test Condition IOL = 1.6mA 1) IOL = 3.2mA 1) IOL = 100E 1) IOL = 200E 1) IOH = IOH = IOH = IOH = -20E -10E -800E 2) -80E 2) max. VIN = 0.45V VIN = 2.0V 0.45 < VIN < VCC fC = 1MHz TA = 25E VCC = 3.6V 4) VCC = 3.6V 5) VCC = 2 ... 3.6V 3) ICC ICC IPD - TBD TBD TBD mA mA E LG Semicon MCU 30 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series DC Characteristics for GMS97L51/52/54/56/58 (Low voltage version) VCC = 3.3 V + 0.3V, - 0.6V; VSS = 0 V; TA = 0E to 70E Limit Values min. Input low voltage Input high voltage Output low voltage Port 1,2,3 Port 0,EA,RESET Port 1,2,3 Port 0,EA,RESET Output high voltage Port 1,2,3 Port 0 in external bus mode, ALE,PSEN Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 12 MHz Idle mode, 12 MHz Power Down Mode VIL VIH VOL 1 VOL 2 VOL 3 VOL 4 VOH 1 VOH 2 VOH 3 VOH 4 IIL ITL ILI CIO -0.5 2.0 2.0 0.9VCC 2.0 0.9VCC -1 -25 0.8 VCC + 0.5 0.45 0.45 0.3 0.3 -50 -250 1 10 Parameter Symbol Unit V V V V V V V V V V E E E pF Test Condition IOL = 1.6mA 1) IOL = 3.2mA 1) IOL = 100E 1) IOL = 200E 1) IOH = IOH = IOH = IOH = -20E -10E -800E 2) -80E 2) max. VIN = 0.45V VIN = 2.0V 0.45 < VIN < VCC fC = 1MHz TA = 25E VCC = 3.6V 4) VCC = 3.6V 5) VCC = 3.6V 3) ICC ICC IPD - 11 5 15 mA mA E MAY. 1998 31 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading: > 50pF at 3.3V, > 100pF at 5V), the noise pulse on ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address lines are stabilizing. 3) IPD (Power Down Mode) is measured under following conditions: EA = Port0 = VCC; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; all other pins are disconnected. 4) ICC (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.; EA = Port0 = RESET = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (appr. 1mA). 5) ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VCC; all other pins are disconnected; 6) ICC max at other frequencies is given by: active mode: ICC = 1.27 fOSC + 5.73 idle mode: ICC = 0.28 fOSC + 1.45 (except OTP devices) where fOSC is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5V. LG Semicon MCU 32 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series AC Characteristics for GMS90 series (12MHz version) Vcc = 5 V : VCC = 5 V + 10%, -15%; VSS = 0 V; TA = 0C to 70C (CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80 pF) Vcc = 3.3 V : VCC = 3.3 V + 0.3 V, -0.6 V; VSS = 0 V; TA = 0C to 70C (CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50 pF) Variable clock : Vcc = 5V : 1/tCLCL = 3.5 MHz to 12 MHz Vcc = 3.3V : 1/tCLCL = 1 MHz to 12 MHz Program Memory Characteristics Limit Values Parameter Symbol 12 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXOX tPXIZ*) tPXAV*) tAVIV tAZPL 127 43 30 58 215 0 75 0 Variable Clock min. 2tCLCL - 40 tCLCL - 40 tCLCL -53 tCLCL - 25 3tCLCL - 35 0 tCLCL - 8 0 4tCLCL - 100 3tCLCL - 100 tCLCL - 20 5tCLCL - 115 - Unit max. 233 150 63 302 - max. ns ns ns ns ns ns ns ns ns ns ns ns *) Interfacing the GMS90 series to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. MAY. 1998 33 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller AC Characteristics for GMS90 series (12MHz version) External Data Memory Characteristics Limit Values Parameter Symbol 12 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 400 400 53 0 200 203 43 33 433 33 - Variable Clock min. 6tCLCL - 100 6tCLCL - 100 tCLCL - 30 0 3tCLCL - 50 4tCLCL - 130 tCLCL - 40 tCLCL - 50 7tCLCL - 150 tCLCL - 50 5tCLCL - 165 2tCLCL - 70 8tCLCL - 150 9tCLCL - 165 3tCLCL +50 tCLCL +40 0 Unit max. 252 97 517 585 300 123 0 max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LG Semicon MCU 34 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Advance Information (12MHz version) External Clock Drive Limit Values Parameter Symbol min. Oscillator period(Vcc=5V) Oscillator period(Vcc=3.3V) High time Low time Rise time Fall time tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL 83.3 83.3 20 20 285.7 1 tCLCL - t CLCX tCLCL - t CHCX 20 20 Variable clock max. Unit ns us ns ns ns ns MAY. 1998 35 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller AC Characteristics for GMS90 series (24MHz version) VCC = 5 V + 10%, - 15%; VSS = 0 V; TA = 0C to 70C (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory characteristics Limit Values Parameter Symbol 24 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL 43 17 17 22 95 0 37 0 Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. 2tCLCL - 40 tCLCL - 25 tCLCL - 25 tCLCL - 20 3tCLCL - 30 0 tCLCL - 5 0 4tCLCL - 87 3tCLCL - 65 tCLCL - 10 5tCLCL - 60 - Unit max. 80 60 32 148 - max. ns ns ns ns ns ns ns ns ns ns ns ns *) Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. LG Semicon MCU 36 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series AC characteristics for GMS90 series (24MHz version) External Data Memory Characteristics Limit Values Parameter Symbol 24 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 180 180 15 0 75 67 17 5 170 15 - Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. 6tCLCL - 70 6tCLCL - 70 tCLCL - 27 0 3tCLCL - 50 4tCLCL - 97 tCLCL - 25 tCLCL - 37 7tCLCL - 122 tCLCL - 27 5tCLCL - 90 2tCLCL - 20 8tCLCL - 133 9tCLCL - 155 3tCLCL + 50 tCLCL + 25 0 Unit max. 118 63 200 220 175 67 0 max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MAY. 1998 37 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Advance Information (24MHz version) External Clock Drive Limit Values Parameter Symbol Variable clock Freq. = 3.5 MHz to 24 MHz min. Oscillator period High time Low time Rise time Fall time tCLCL tCHCX tCLCX tCLCH tCHCL 41.7 12 12 - Unit max. 285.7 tCLCL - t CLCX tCLCL - t CHCX 12 12 ns ns ns ns ns LG Semicon MCU 38 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series AC Characteristics for GMS90 series (33MHz version) VCC = 5 V + 10%, -15%; VSS = 0 V; TA = 0 C to 70 C (CL for port 0, ALE and PSEN outputs = 100pF; CL for all other outputs =80pF) Program Memory Characteristics Limit Values Parameter Symbol 33 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL 40 10 10 15 80 0 25 0 Variable Clock 1/tCLCL = 3.5 MHz to 33 MHz min. 2tCLCL - 20 tCLCL - 20 tCLCL - 20 tCLCL - 15 3tCLCL - 20 0 tCLCL - 5 0 4tCLCL - 65 3tCLCL - 55 tCLCL - 10 5tCLCL - 60 - Unit max. 56 35 20 91 - max. ns ns ns ns ns ns ns ns ns ns ns ns *) Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. MAY. 1998 39 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller AC Characteristics for GMS90series (33MHz version) External Data Memory Characteristics Limit Values Parameter Symbol 33 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 132 132 10 0 71 66 10 5 142 10 - Variable Clock 1/tCLCL = 3.5 MHz to 33 MHz min. 6tCLCL - 50 6tCLCL - 50 tCLCL - 20 0 3tCLCL - 20 4tCLCL - 55 tCLCL - 20 tCLCL - 25 7tCLCL - 70 tCLCL - 20 5tCLCL - 70 2tCLCL - 15 8tCLCL - 90 9tCLCL - 90 3tCLCL + 20 tCLCL + 20 0 Unit max. 81 46 153 183 111 40 0 max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LG Semicon MCU 40 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Advance Information (33MHz version) External Clock Drive Limit Values Parameter Symbol Variable clock Freq. = 3.5 MHz to 33 MHz min. Oscillator period High time Low time Rise time Fall time tCLCL tCHCX tCLCX tCLCH tCHCL 30.3 11.5 11.5 - Unit max. 285.7 tCLCL - t CLCX tCLCL - t CHCX 5 5 ns ns ns ns ns MAY. 1998 41 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller AC Characteristics for GMS90 series (40MHz version) VCC = 5 V + 10%, -15%; VSS = 0 V; TA = 0 C to 70 C (CL for port 0, ALE and PSEN outputs = 100pF; CL for all other outputs =80pF) Program Memory Characteristics Limit Values Parameter Symbol 40 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL 35 10 10 10 60 0 20 -50 Variable Clock 1/tCLCL = 3.5 MHz to 40 MHz min. 2tCLCL - 15 tCLCL - 15 tCLCL - 15 tCLCL - 15 3tCLCL - 15 0 tCLCL - 5 -5 4tCLCL - 45 3tCLCL - 50 tCLCL - 10 5tCLCL - 60 - Unit max. 55 25 15 65 - max. ns ns ns ns ns ns ns ns ns ns ns ns *) Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. LG Semicon MCU 42 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series AC Characteristics for GMS90series (40MHz version) External Data Memory Characteristics Limit Values Parameter Symbol 40 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 120 120 10 0 60 70 10 5 125 5 - Variable Clock 1/tCLCL = 3.5 MHz to 40 MHz min. 6tCLCL - 30 6tCLCL - 30 tCLCL - 15 0 3tCLCL - 15 4tCLCL - 30 tCLCL - 15 tCLCL - 20 7tCLCL - 50 tCLCL - 20 5tCLCL - 50 2tCLCL - 12 8tCLCL - 50 9tCLCL - 75 3tCLCL + 15 tCLCL + 15 0 Unit max. 75 38 150 150 90 40 0 max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MAY. 1998 43 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Advance Information (40MHz version) External Clock Drive Limit Values Parameter Symbol Variable clock Freq. = 3.5 MHz to 40 MHz min. Oscillator period High time Low time Rise time Fall time tCLCL tCHCX tCLCX tCLCH tCHCL 25 10 10 - Unit max. 285.7 tCLCL - t CLCX tCLCL - t CHCX 10 10 ns ns ns ns ns LG Semicon MCU 44 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Figure 4 Program Memory Read Cycle MAY. 1998 45 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Figure 5 Data Memory Read Cycle LG Semicon MCU 46 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Figure 6 Data Memory Write Cycle MAY. 1998 47 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller OTP ROM Verification Characteristics ROM Verification Mode 1 Parameter Address to valid data ENABLE to valid data Data float after ENABLE Oscillator frequency Symbol min. tAVQV tELQV tEHQZ 1/tCLCL 0 4 48tCLCL 48tCLCL 48tCLCL 6 Limit Values max. ns ns ns MHz Unit P1.0~P1.7 P2.0~P2.5 P3.4 tAVQV Port 0 High-Z Address Valid Output tEHQZ tELQV P2.7 ENABLE Address: P1.0 - P1.7 = A0 - A7 P2.0 - P2.5 = A8 - A13 P3.4 = A14 Data: P0.0 - P0.7 = D0 - D7 Inputs: P2.6, PSEN=VSS ALE, EA = VIH RESET = VIH1 Figure 7 OTP ROM Verification Mode 1 LG Semicon MCU 48 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series VCC - 0.5 V 0.2VCC + 0.9 Test Point 0.2VCC - 0.1 0.45 V AC Inputs during testing are driven at VCC - 0.5V for a logic "1" and 0.45V for a logic "0". Timing measurements are made at VIHmin for a logic "1" and VILmax for a logic "0". Figure 8 AC Testing : Input, Output Waveforms VLOAD + 0.1 VLOAD VLOAD - 0.1 Timing Reference Point 0.2VCC - 0.1 VOH - 0.1 VOL + 0.1 For timing purposes a port pin is no longer floating when a 100mV change from load voltage occurs and begins to float when a 100mV change from the loaded VOH / VOL level occurs. IOL / IOH A 20mA. Figure 9 AC Testing : Float Waveforms Figure 10 External Clock Cycle MAY. 1998 49 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Crystal Oscillator Mode Driving from External Source C1 1~40MHz XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14 N.C. XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14 C2 XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15 External Oscillator Signal XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15 Recommend: C1,C2 = 30 pF 10 pF (Include stray capacitance) Figure 11 Recommended Oscillator Circuits EPROM Characteristics The GMS97C5x, 97L5x are programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for Vpp (programming supply voltage) and in the width and number of the ALE/PROG pulses. The GMS97C5x, 97L5x contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an manufactured by LGS. Table 11 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 12 and 13. Figure 14 shows the circuit configuration for normal program memory verification. LG Semicon MCU 50 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Quick-pulse programming The setup for microcontroller quick-pulse programming is shown in Figure 13. Note that the GMS97C5x, 97L5x is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 12. The code byte to be programmed into that location is applied to port 0, RST, PSEN and pins of port 2 and 3 in Table 11 are held at the "Program Data" levels indicated in Table 11. The ALE/PROG is pulsed low 25 times as shown Figure 13. To program the encryption table, repeat the 25 pulses (10 pulses for 97x54/56/58) programming sequence for addresses 0 through 1FH(3FH for 97x54/56/58), using the "Pgm Encryption Table" levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 25 pulses (10 pulses for 97x54/56/58) programming sequence using the "Pgm Security Bit" levels after one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified Vpp level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free glitches and overshoot. Program Verification If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory location to be read is applied to ports 1 and 2 as shown in Figure 15. The other pins are held at the "Verify Code Data" levels indicated in Table 11. The contents of the address location will be emitted on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Program Memory Lock Bits The two-level Program Lock system consists of 2 Lock bits and a 32-byte (64-byte for GMS97x54/56/58) Encryption Array which are used to protect the program memory against software piracy. Encryption Array: Lock Bit Protection Modes Within the EPROM array are 32 bytes (64 bytes for Program Lock Bits GMS97x54/56/58) of Encryption Array that are initially Protection Type unprogrammed (all 1s). Every time that a byte is LB1 LB2 addressed during a verify, address lines are used to 1 U U No program lock features select a byte of the Encryption array. This byte is then exclusive-NORed (XNOR) with the code byte, creating an Futher programming of the 2 P U Encrypted Verify byte. EPROM is disabled The algorithm, with the array in the unprogrammed state Same as mode 2, also verify (all 1s), will return the code in its original, unmodified form, 3 P P is disabled It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as U: unprogrammed, P: programmed well. MAY. 1998 51 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Reading the Signature Bytes : The GMS97x51/52 signature bytes in locations 030H and 031H, the GMS97x54/56/58 signature bytes in locations 030H and 060H. To read these bytes follow the procedure for EPROM verify, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: Location 30H 31H All GMS97C51/L51 GMS97C52/L52 60H GMS97C54/L54 GMS97C56/L56 GMS97C58/L58 Device Contents E0H 73H 71H 54H 56H 58H Program / Verify algorithms Any algorithm in agreement with the conditions listed in Table 11, and which satisfies the timing specifications is suitable. Table 11. EPROM programming modes MODE Read Signature Program Code Data Verify Code Data Program encryption table Program security bit 1 Program security bit 2 RST 1 1 1 1 1 1 PSEN 0 0 0 0 0 0 ALE/PROG 1 0 1 0 0 0 EA/VPP 1 VPP 1 VPP VPP VPP P2.7 0 1 0 1 1 1 P2.6 0 0 0 0 1 1 P3.7 0 1 1 1 1 0 P3.6 0 1 1 0 1 0 Notes : 1. "0" = Valid low for that pin, "1" = valid high for that pin. 2. Vpp = 12.75V 0.25V 3. Vcc = 5V 10% during programming and verification. 4. ALE/PROG receives 25 (10 for GMS97x54/56/58) programming pulses while VPP is held at 12.75. Each programming pulse is low for 100us ( 10us) and high for a minimum of 10us. LG Semicon MCU 52 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series or 10 P2.0~P2.5 P3.4 A8~A13 A14 Figure 12 Programming Configuration 25 Pulses In the GMS97x51/52 ALE/PROG 10uS min. Enlarged view 100uS 10 100uS 10 10 Pulses In the GMS97x54/56/58 ALE/PROG Figure 13 PROG Waveform MAY. 1998 53 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller P2.0~P2.5 P3.4 A8~A13 A14 Figure 14 Program Verification LG Semicon MCU 54 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series EPROM Programming and Verification Characteristics TA = 21E to 27E Vcc = 5V 10%, Vss = 0V (See Figure 15) Parameter Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data setup after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low Symbol min. VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGL tAVQL tELQZ tEHQZ tGHGL 12.5 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 0 10 Limit Values max. 13.0 50 6 110 48tCLCL 48tCLCL 48tCLCL V mA MHz us us us us Unit MAY. 1998 55 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller P1.0~P1.7 P2.0~P2.5 P3.4 For programming verification see Figure 12. For verification conditions see Figure 14. Figure 15 EPROM Programming and Verification LG Semicon MCU 56 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Plastic Package, P-LCC-44-SMD (Plastic Leaded Chip-Carrier) 1) Does not include plastic or metal protrusions of 0.15 max per side Dimensions in mm SMD = Surface Mounted Device SMD = Surface Mounted Device MAY. 1998 57 LG Semicon MCU GMS90 Series 8-Bit CMOS Microcontroller Plastic Package, P-DIP-40 (Plastic Dual in-Line Package) Dimensions in mm LG Semicon MCU 58 MAY. 1998 8-Bit CMOS Microcontroller GMS90 Series Plastic Package, P-MQFP-44(SMD) (Plastic Metric Quad Flat Package) * Does not include plastic or metal protrusions of 0.25 max per side Dimensions in mm MAY. 1998 59 LG Semicon MCU |
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